The present invention relates to clock networks and associated registers for use with programmable logic devices or other similar devices.
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements (i.e. circuits that perform logic functions), sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). The term LAB as used herein will be considered broad enough to refer generally to a grouping of logic circuits. LABs will typically include a plurality of clocked registers such as, e.g., latches or flip-flops, that load and/or output data (i.e. “move” data) in response to a clock signal. A clock distribution network typically exists that distributes one or more clock signals from one or more clock signal sources to the clocked registers on the PLD.
In a typical PLD, each LAB can generate a small number of clock signals from which each of the LAB's logic elements can chose to trigger its associated register on, for example, a rising edge of the clock signal. The LABs generate these clock signals from a general clock signal that is either routed through the general interconnect or through a set of high-speed dedicated clock lines that are global to the device.
Because they typically fan out to every logic element in the device, clock networks can consume considerable power. In general, the power dissipation is proportional to the switching frequency of the clock. Some of this power dissipation occurs in the wiring and driving transistors of the global clock network outside and between the LABs, and some of the power dissipation occurs in the wiring and devices that exist inside each LAB and its associated logic elements.